Filter
Top Products
Preface
xii Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B
Note
Angle brackets can also enclose a permitted range of values. The
example, <0-3>, shows that in name extensions, only one of the
values 0, 1, 2, or 3 is valid.
Timing diagrams
The figure named Key to timing diagram conventions explains the components used in
timing diagrams. Variations, when they occur, have clear labels. You must not assume
any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value
within the shaded area at that time. The actual level is unimportant and does not affect
normal operation.
Key to timing diagram conventions
Signals
The signal conventions are:
Signal level The level of an asserted signal depends on whether the signal is
active-HIGH or active-LOW. Asserted means HIGH for
active-HIGH signals and LOW for active-LOW signals.
Lower-case n Denotes an active-LOW signal.
Prefix A Denotes global Advanced eXtensible Interface (AXI) signals.
Prefix AR Denotes AXI read address channel signals.
Prefix AW Denotes AXI write address channel signals.
&ORFN
+,*+WR/2:
7UDQVLHQW
+,*+/2:WR+,*+
%XVVWDEOH
%XVWRKLJKLPSHGDQFH
%XVFKDQJH
+LJKLPSHGDQFHWRVWDEOHEXV