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Functional Overview
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-9
If transfers are described as non-bufferable then the bridge must wait for the write
response to indicate that the transfer has been completed to memory. If numerous
bufferable writes are performed, followed by a non-bufferable write, then the bridge
must wait until it receives the write response associated with the final write.
Read after write hazard detection buffer
A RAW hazard detection buffer avoids potential RAW hazards. The protocol used
internally to AHB MC does not perform memory coherency checks to catch Write After
Read (WAR) or RAW hazards.
Because of the nature of the AHB protocol, WAR hazards never occur because the read
must have completed before the write can be accepted.
Because the bridge permits writes to be buffered internally, there is a potential for a
RAW hazard to occur. If you perform a bufferable write then it might not complete
immediately. If a read to that same memory location is performed then both transfers
can be in the queue and the internal memory controller can reorder these transactions
for performance reasons so that the read occurs before the write. This means that the
data read might be the value before the most recent write. The bridge has to detect these
potential cases and stall the read transfer until any buffered writes that might cause a
RAW hazard have been completed.
The bridge contains logic to monitor up to four outstanding write addresses. If an
incoming read occurs to a 4KB region that has been written to, then it is stalled. If four
bufferable writes occur then the AHB is stalled until a response is seen for the first of
the four writes in the buffer.
AHB response signals
The interconnect used within the AHB MC contains many combinatorial paths that link
different AHB input ports. To improve the synthesis timing, the AHB responses are
registered to limit these paths to within the design.
Locked transfers
AHB MC supports locked transfers, within a 512MB region. This is because of the way
the interconnect processes locked transfers. There is a significant performance penalty
in using locked transfers. Transfers that are locked together wait for all other ports to
complete any outstanding transfers before they can begin. While a locked sequence
occurs to a specific 512MB memory region, all other access to that region is stalled. All
locked writes are processed as non-bufferable writes and so have to wait for the
appropriate write response before indicating their completion.