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Introduction
1-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B
1.1.3 SMC
The SMC is a high-performance, area-optimized SRAM memory controller.
The SMC is pre-configured and validated for:
• the SRAM memory type
• the number of SRAM memory devices
• the maximum SRAM memory width.
The SRAM memory interface type is defined as supporting:
• synchronous or asynchronous SRAM
• Pseudo Static Random Access Memory (PSRAM)
• NOR flash
• NAND flash devices with an SRAM interface.
The SMC block offers the following features:
• it is configured to support the maximum SRAM memory data width of 32-bit
• programmable cycle timings, and memory width per chip select
• atomic switching of memory device and controller operating modes
• support for the PL220 External Bus Interface (EBI) PrimeCell, enabling sharing
of external address and data bus pins between memory controller interfaces
• support for a low-power interface
• support for a remap signal
• support for clock domains to be synchronous or asynchronous
See Chapter 2 Functional Overview for more information.
1.1.4 Clock domains
The memory controller has two clock domains:
• AHB clock domain
• static memory clock domain.
See Chapter 2 Functional Overview for more information.
1.1.5 Low-power interfaces
The memory controller has two low-power interfaces, one for each clock domain.
See Chapter 2 Functional Overview for more information.