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Functional Overview
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-19
smc_msync0
When HIGH, indicates smc_mclk0 is synchronous to smc_aclk.
Otherwise they are asynchronous. Ensure that smc_msync0 is tied to the
same value as smc_async0.
smc_rst_bypass
Use this signal for ATPG testing only. Tie it LOW for normal operation.
smc_use_ebi
When HIGH, indicates that the SMC must operate with a PrimeCell EBI.
See the ARM PrimeCell External Bus Interface (PL220) Technical
Reference Manual.
2.4.4 APB slave interface operation
To enable a clean registered interface to the external infrastructure, the APB interface
always adds a wait state for all reads and writes by driving pready LOW during the first
cycle of the access phase.
In two instances, a delay of more than one wait state can be generated:
• when a direct command is received and there are outstanding commands that
prevent a new command being stored in the command FIFO
• when an APB access is received and a previous direct command has not
completed.
2.4.5 Format block
This section describes:
• Hazard handling
• SRAM memory accesses on page 2-20.
Hazard handling
There are four types of hazard:
• Read After Read (RAR)
• Write After Write (WAW)
• Read After Write (RAW)
• Write After Read (WAR).
The AHB interface deals with RAW hazards. WAR hazards do not occur in the AHB.