Functional Overview
2-16 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B
The state transitions are:
Ready to Reset
When reset is asserted to the smc_aclk domain, it enters the Reset
state.
Reset to Ready
When reset is deasserted to the smc_aclk domain, it enters the
Ready state.
Ready to Low-power
The Low-power state is entered when the SMC next becomes idle
after either:
• the SMC receives a low-power request through the APB
smc_memc_cfg_set Register
• the SMC receives a low-power request through the SMC
low-power interface.
Low-power to Ready
The SMC exits the Low-power state back to Ready when either:
• the SMC low-power request bit is cleared in the APB
smc_memc_cfg_clr Register
• the SMC low-power interface negates the low-power
request.
Low-power to Reset
When Reset is asserted to the smc_aclk reset domain, it enters the
Reset state.
2.4.2 Clocking and resets
This section describes:
• Clocking
• Resets on page 2-17.
Clocking
All configurations of the SMC support at least two clock domains, and have the
following clock inputs:
• smc_aclk
• smc_mclk0
• smc_mclk0n.
