Filter
Top Products
9-3
Circuit Description
The CPU board contains the microprocessor
system. All display, front panel, disk, and comput-
er interfaces are on this board.
MICROPROCESSOR SYSTEM
The microprocessor, U101, is an 80C186 micro-
controller which integrates a fast 16 bit processor,
counter-timers, interrupt controller, DMA controller,
and I/O decoding into a single component.
The 80C186 uses a 24.00 MHz crystal, X101, as
its oscillator. The instruction clock cycle is 2 oscil-
lator cycles or 12.0 MHz. The data and lower 16
bits of address are multiplexed on AD0-AD15.
U201, U202, U203 latch the address A0-A19 at
the beginning of each memory or I/O cycle. U204
and U205 are bidirectional data bus drivers which
are active during the data read/write portion of
each memory or I/O cycle.
The 80C186 can address 1 Mbyte of memory and
64k of I/O space. The memory is mapped into 4
256kbyte blocks. Each block has 2 sockets, one
for the low byte and one for the high byte of data.
U301 and U302 are 128kbyte EPROMS holding
the program boot firmware. This memory is
mapped at C0000H to FFFFFH (256k). U303 and
U304 are 128kbyte data ROMS mapped at
80000H to BFFFFH (256k).
U401-403 are 128kbyte CMOS static RAMs
mapped at 00000H to 7FFFFH (512k). U401 and
U402 are backed up by the battery. Q401 provides
power down RAM protection. This memory is
system memory.
4 of the 7 80C186's peripheral chip select strobes
are used by peripherals on the CPU board. -PCS0
is decoded into 16 I/O strobes which access the
clock, keypad, keyboard, knob, printer port, etc. -
PCS1 decodes the disk controller, the GPIB con-
troller, and DMA acknowledge strobes. -PCS2
selects the UART and -PCS3 selects the video
graphics controller. Whenever the video controller
is accessed, the ARDY line is asserted (U504A)
which puts the processor into a wait state. When
the video controller acknowledges the data trans-
fer by pulling -Video_Rdy low, the ARDY line is
de-asserted (U805A and U815D) and the proces-
sor moves on to the next instruction.
Interrupts generated by peripherals on the CPU
board are combined in U505 into a single priori-
tized interrupt. The highest priority pending inter-
rupt will be encoded on U505's outputs and read
via the status port, U608. The UART directly inter-
rupts the processor since it can never be masked.
KEYPAD INTERFACE
The keypad is organized as 8 columns and 8 rows
of switch closures. The conductive rubber keys
provide the switch closures. U607 strobes the col-
umns and U606 detects the switch closure. The
diodes D601 - D608 prevent one column from
affecting another. All of the outputs from U607 are
set high and U606 is read periodically by the pro-
cessor. As long as 00H is read, no key is pressed
and the strobes are left on. When a non-zero byte
is read, then the key strobes are activated individ-
ually in order to decode which key is down.
KEYBOARD INTERFACE
The PC keyboard interface uses U603 to convert
serial data from the keyboard into a parallel byte
for the processor to read. The data format from the
keyboard is a leading start bit followed by 8 data
bits. U603 is reset by a processor read. When a
key is pressed, the bits are shifted into U603.
When the start bit appears at the QH output, 7 bits
of the data byte are in U603. U601 is the 9th bit of
the shift register. When U601 clocks in the start
bit, U601 must have the 8 bits of the data. U601
then latches the serial data in U601 and interrupts
the processor.
Only keyboards which operate in the PC or 8088
mode will function with this interface.
SPIN KNOB
The knob is an optical encoder buffered by U612.
Each transition of its outputs is clocked into U610
or U611 and generates an interrupt at the output
of U602A. The processor keeps track of the knob's
position continuously.
CPU BOARD