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connection between the PCI bus and all other I/O functions. In addition, the PCIO
ASIC contains an embedded Ethernet controller to manage Ethernet transactions and
provides the electrical connection to slower on-board functions, such as the flash
PROM and the audio module.
C.1.12.4 U2P
The UPA-to-PCI bridge (U2P) ASIC provides an I/O connection between the UPA
bus and the two PCI buses. The U2P ASIC features include:
Full master and slave port connection to the high-speed UPA interconnect. The
UPA is a split address/data packet-switched bus that has a potential data
throughput rate of greater than 1 Gbyte per second. UPA data is ECC protected.
Two physically separate PCI bus segments with full master and slave support:
66-MHz PCI bus segment (PCI bus A): 3.3-VDC I/O signaling, 64-bit data bus,
compatible with the PCI 66-MHz extensions, support for up to four master devices
(at 33 MHz only)
33-MHz PCI bus segment (PCI bus B): 5.0-VDC I/O signaling, 64-bit data bus,
support for up to six master devices
Two separate 16-entry streaming caches, one for each bus segment, for accelerating
some kinds of PCI DVMA activity. Single IOMMU with 16-entry TLB for mapping
DVMA addresses for both buses (IOMMU used to translate 32-bit or 64-bit PCI
addresses into 41-bit UPA addresses).
A mondo-vector dispatch unit for delivering interrupt requests to CPU modules,
including support for PCI interrupts from up to six slots, as well as interrupts
from on-board I/O devices.
C.1.12.5 FBC
The frame buffer controller (FBC) ASIC is the graphics draw ASIC that provides
interface between the UPA and the 3DRAM. The FBC ASIC provides 2D and 3D
graphics draw acceleration. Highlights of the FBC ASIC features include:
UPA slave device with write-mostly philosophy
Interfaces with 3DRAM to achieve accelerated graphics performance
Supports single buffered and DBZ configurations
Supports frame buffer-to-frame buffer copy
Supports viewport clipping, picking, and pixel processing
Supports byte, plane masks, raster operations, blend operations, and conditional
writes in 3DRAM
83.3-MHz UPA operation and 75-MHz 3DRAM operation
3.3-VDC and 5-VDC (for RAMDAC ASIC) supply voltage
Functional Description 273