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EMAC Module Registers
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5.31 Emulation Control Register (EMCONTROL)
The emulation control register (EMCONTROL) is shown in Figure 69 and described in Table 68.
Figure 69. Emulation Control Register (EMCONTROL)
31 16
Reserved
R-0
15 2 1 0
Reserved SOFT FREE
R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 68. Emulation Control Register (EMCONTROL) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 SOFT Emulation soft bit. This bit is used in conjunction with FREE bit to determine the emulation suspend
mode. This bit has no effect if FREE = 1.
0 Soft mode is disabled. EMAC stops immediately during emulation halt.
1 Soft mode is enabled. During emulation halt, EMAC stops after completion of current operation.
0 FREE Emulation free bit. This bit is used in conjunction with SOFT bit to determine the emulation suspend
mode.
0 Free-running mode is disabled. During emulation halt, SOFT bit determines operation of EMAC.
1 Free-running mode is enabled. During emulation halt, EMAC continues to operate.
5.32 FIFO Control Register (FIFOCONTROL)
The FIFO control register (FIFOCONTROL) is shown in Figure 70 and described in Table 69.
Figure 70. FIFO Control Register (FIFOCONTROL)
31 16
Reserved
R-0
15 2 1 0
Reserved TXCELLTHRESH
R-0 R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 69. FIFO Control Register (FIFOCONTROL) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1-0 TXCELLTHRESH 0-3h Transmit FIFO cell threshold. Indicates the number of 64-byte packet cells required to be in the
transmit FIFO before the packet transfer is initiated. Packets with fewer cells will be initiated when
the complete packet is contained in the FIFO. The default value is 2, but 3 is also valid. 0 and 1 are
not valid values.
0-1h Not a valid value.
2h Two 64-byte packet cells required to be in the transmit FIFO.
3h Three 64-byte packet cells required to be in the transmit FIFO.
114
EMAC/MDIO Module SPRUFL5B–April 2011
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