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User's Guide
SPRUFL5B–April 2011
EMAC/MDIO Module
1 Introduction
This document provides a functional description of the Ethernet Media Access Controller (EMAC) and
physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the device.
Included are the features of the EMAC and MDIO modules, a discussion of their architecture and
operation, how these modules connect to the outside world, and a description of the registers for each
module.
The EMAC controls the flow of packet data from the system to the PHY. The MDIO module controls PHY
configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the system core through a custom interface that
allows efficient data transmission and reception. This custom interface is referred to as the EMAC control
module and is considered integral to the EMAC/MDIO peripheral.
1.1 Purpose of the Peripheral
The EMAC module is used to move data between the device and another host connected to the same
network, in compliance with the Ethernet protocol.
1.2 Features
The EMAC/MDIO has the following features:
• Synchronous 10/100 Mbps operation.
• Standard Media Independent Interface (MII) and/or Reduced Media Independent Interface (RMII) to
physical layer device (PHY).
• EMAC acts as DMA master to either internal or external device memory space.
• Eight receive channels with VLAN tag discrimination for receive quality-of-service (QOS) support.
• Eight transmit channels with round-robin or fixed priority for transmit quality-of-service (QOS) support.
• Ether-Stats and 802.3-Stats statistics gathering.
• Transmit CRC generation selectable on a per channel basis.
• Broadcast frames selection for reception on a single channel.
• Multicast frames selection for reception on a single channel.
• Promiscuous receive mode frames selection for reception on a single channel (all frames, all good
frames, short frames, error frames).
• Hardware flow control.
• 8k-byte local EMAC descriptor memory that allows the peripheral to operate on descriptors without
affecting the CPU. The descriptor memory holds enough information to transfer up to 512 Ethernet
packets without CPU intervention. (This memory is also known as CPPI RAM.)
• Programmable interrupt logic permits the software driver to restrict the generation of back-to-back
interrupts, which allows more work to be performed in a single call to the interrupt service routine.
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EMAC/MDIO Module SPRUFL5B–April 2011
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