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EMAC Control Module Registers
3.11 EMAC Control Module Interrupt Core Miscellaneous Interrupt Status Registers
(C0MISCSTAT-C2MISCSTAT)
The EMAC control module interrupt core 0-2 miscellaneous interrupt status register (CnMISCSTAT) is
shown in Figure 22 and described in Table 19
Figure 22. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register
(CnMISCSTAT)
31 16
Reserved
R-0
15 4 3 2 1 0
Reserved STATPENDSTAT HOSTPENDSTAT LINKINT0STAT USERINT0STAT
R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 19. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register
(CnMISCSTAT)
Bit Field Value Description
31-4 Reserved 0 Reserved
3 STATPENDSTAT Interrupt status for EMAC STATPEND masked by the CnMISCEN register
0 EMAC STATPEND does not satisfy conditions to generate a CnMISCPULSE interrupt.
1 EMAC STATPEND satisfies conditions to generate a CnMISCPULSE interrupt.
2 HOSTPENDSTAT Interrupt status for EMAC HOSTPEND masked by the CnMISCEN register
0 EMAC HOSTPEND does not satisfy conditions to generate a CnMISCPULSE interrupt.
1 EMAC HOSTPEND satisfies conditions to generate a CnMISCPULSE interrupt.
1 LINKINT0STAT Interrupt status for MDIO LINKINT0 masked by the CnMISCEN register
0 MDIO LINKINT0 does not satisfy conditions to generate a CnMISCPULSE interrupt.
1 MDIO LINKINT0 satisfies conditions to generate a CnMISCPULSE interrupt.
0 USERINT0STAT Interrupt status for MDIO USERINT0 masked by the CnMISCEN register
0 MDIO USERINT0 does not satisfy conditions to generate a CnMISCPULSE interrupt.
1 MDIO USERINT0 satisfies conditions to generate a CnMISCPULSE interrupt.
67
SPRUFL5B–April 2011 EMAC/MDIO Module
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