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MDIO Registers
4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in
Figure 33 and described in Table 31.
Figure 33. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
31 16
Reserved
R-0
15 2 1 0
Reserved USERACCESS1 USERACCESS0
R-0 R/W1S-0 R/W1S-0
LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing a 0 has no effect); -n = value after reset
Table 31. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 USERACCESS1 MDIO user interrupt mask set for USERINTMASKED[1]. Setting a bit to 1 will enable MDIO user
command complete interrupts for the USERACCESS1 register. MDIO user interrupt for
USERACCESS1 is disabled if the corresponding bit is 0. Writing a 0 to this bit has no effect.
0 MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is
disabled.
1 MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is
enabled.
0 USERACCESS0 MDIO user interrupt mask set for USERINTMASKED[0]. Setting a bit to 1 will enable MDIO user
command complete interrupts for the USERACCESS0 register. MDIO user interrupt for
USERACCESS0 is disabled if the corresponding bit is 0. Writing a 0 to this bit has no effect.
0 MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is
disabled.
1 MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is
enabled.
77
SPRUFL5B–April 2011 EMAC/MDIO Module
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