Filter
Top Products
www.ti.com
EMAC Control Module Registers
3.13 EMAC Control Module Interrupt Core Transmit Interrupts Per Millisecond Registers
(C0TXIMAX-C2TXIMAX)
The EMAC control module interrupt core 0-2 transmit interrupts per millisecond register (CnTXIMAX) is
shown in Figure 24 and described in Table 21
Figure 24. EMAC Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register
(CnTXIMAX)
31 16
Reserved
R-0
15 6 5 0
Reserved TXIMAX
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21. EMAC Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register
(CnTXIMAX)
Bit Field Value Description
31-6 Reserved 0 Reserved
5-0 TXIMAX 2-3Fh TXIMAX is the desired number of CnTXPULSE interrupts generated per millisecond when
CnTXPACEEN is enabled in INTCONTROL.
The pacing mechanism can be described by the following pseudo-code:
while(1) {
interrupt_count = 0;
/* Count interrupts over a 1ms window */
for(i = 0; i < INTCONTROL[INTPRESCALE]*250; i++) {
interrupt_count += NEW_INTERRUPT_EVENTS();
if(i < INTCONTROL[INTPRESCALE]*pace_counter)
BLOCK_EMAC_INTERRUPTS();
else
ALLOW_EMAC_INTERRUPTS();
}
ALLOW_EMAC_INTERRUPTS();
if(interrupt_count > 2*TXIMAX)
pace_counter = 255;
else if(interrupt_count > 1.5*TXIMAX)
pace_counter = previous_pace_counter*2 + 1;
else if(interrupt_count > 1.0*TXIMAX)
pace_counter = previous_pace_counter + 1;
else if(interrupt_count > 0.5*TXIMAX)
pace_counter = previous_pace_counter - 1;
else if(interrupt_count != 0)
pace_counter = previous_pace_counter/2;
else
pace_counter = 0;
previous_pace_counter = pace_counter;
}
69
SPRUFL5B–April 2011 EMAC/MDIO Module
Submit Documentation Feedback
© 2011, Texas Instruments Incorporated