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46 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ..................................... 92
47 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions............................... 93
48 MAC Input Vector Register (MACINVECTOR) Field Descriptions.................................................. 94
49 MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions................................... 95
50 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions ......................... 96
51 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions........................ 97
52 Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions ..................................... 98
53 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions ............................... 99
54 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions ......................... 100
55 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions........................ 100
56 MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions ..................................... 101
57 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions ............................... 101
58 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field
Descriptions............................................................................................................... 102
59 Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions ................................... 105
60 Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions ...................................... 106
61 Receive Maximum Length Register (RXMAXLEN) Field Descriptions............................................ 107
62 Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions....................................... 107
63 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions ...... 108
64 Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions.............. 108
65 Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions ..................... 109
66 MAC Control Register (MACCONTROL) Field Descriptions ....................................................... 110
67 MAC Status Register (MACSTATUS) Field Descriptions........................................................... 112
68 Emulation Control Register (EMCONTROL) Field Descriptions ................................................... 114
69 FIFO Control Register (FIFOCONTROL) Field Descriptions....................................................... 114
70 MAC Configuration Register (MACCONFIG) Field Descriptions .................................................. 115
71 Soft Reset Register (SOFTRESET) Field Descriptions............................................................. 115
72 MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions ........................... 116
73 MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions............................ 116
74 MAC Hash Address Register 1 (MACHASH1) Field Descriptions................................................. 117
75 MAC Hash Address Register 2 (MACHASH2) Field Descriptions................................................. 117
76 Back Off Test Register (BOFFTEST) Field Descriptions ........................................................... 118
77 Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions .................................... 118
78 Receive Pause Timer Register (RXPAUSE) Field Descriptions................................................... 119
79 Transmit Pause Timer Register (TXPAUSE) Field Descriptions .................................................. 119
80 MAC Address Low Bytes Register (MACADDRLO) Field Descriptions .......................................... 120
81 MAC Address High Bytes Register (MACADDRHI) Field Descriptions........................................... 121
82 MAC Index Register (MACINDEX) Field Descriptions .............................................................. 121
83 Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions................... 122
84 Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions ................... 122
85 Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions.................................. 123
86 Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions .................................. 123
87 Physical Layer Definitions .............................................................................................. 134
88 Document Revision History............................................................................................. 135
9
SPRUFL5B–April 2011 List of Tables
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