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2.6.3 Interrupt Control
Interrupt conditions generated by the EMAC and MDIO modules are combined into four interrupt signals
that are routed to three independent interrupt cores in the EMAC control module; the interrupt cores then
relay the interrupt signals to the CPU interrupt controller. The EMAC control module uses two sets of
registers to control the interrupt signals to the CPU:
• CnRXTHRESHEN, CnRXEN, CnTXEN, and CnMISCEN registers enable the interrupt core pulse
signals that are mapped to the CPU interrupt controller
• INTCONTROL, CnRXIMAX, and CnTXIMAX registers enable interrupt pacing to limit the number of
interrupt pulses generated per millisecond
Interrupts must be acknowledged by writing the appropriate value to the EMAC End-Of-Interrupt Vector
(MACEOIVECTOR). The MACEOIVECTOR behaves as an interrupt pulse interlock -- once the EMAC
control module has issued an interrupt pulse to the CPU, it will not generate further pulses of the same
type until the original pulse has been acknowledged.
2.7 MDIO Module
The MDIO module is used to manage up to 32 physical layer (PHY) devices connected to the Ethernet
Media Access Controller (EMAC). The device supports a single PHY being connected to the EMAC at any
given time. The MDIO module is designed to allow almost transparent operation of the MDIO interface
with little maintenance from the CPU.
The MDIO module continuously polls 32 MDIO addresses in order to enumerate all PHY devices in the
system. Once a PHY device has been detected, the MDIO module reads the MDIO PHY link status
register (LINK) to monitor the PHY link state. Link change events are stored in the MDIO module, which
can interrupt the CPU. This storing of the events allows the CPU to poll the link status of the PHY device
without continuously performing MDIO module accesses. However, when the CPU must access the MDIO
module for configuration and negotiation, the MDIO module performs the MDIO read or write operation
independent of the CPU. This independent operation allows the processor to poll for completion or
interrupt the CPU once the operation has completed.
The MDIO module does not support the "Clause 45" interface.
2.7.1 MDIO Module Components
The MDIO module (Figure 10) interfaces to the PHY components through two MDIO pins (MDIO_CLK and
MDIO), and to the CPU through the EMAC control module and the configuration bus. The MDIO module
consists of the following logical components:
• MDIO clock generator
• Global PHY detection and link state monitoring
• Active PHY monitoring
• PHY register user access
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EMAC/MDIO Module SPRUFL5B–April 2011
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