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List of Figures
1 EMAC and MDIO Block Diagram........................................................................................ 13
2 Ethernet Configuration—MII Connections.............................................................................. 15
3 Ethernet Configuration—RMII Connections............................................................................ 16
4 Ethernet Frame Format................................................................................................... 17
5 Basic Descriptor Format.................................................................................................. 18
6 Typical Descriptor Linked List............................................................................................ 19
7 Transmit Buffer Descriptor Format ...................................................................................... 22
8 Receive Buffer Descriptor Format....................................................................................... 25
9 EMAC Control Module Block Diagram.................................................................................. 29
10 MDIO Module Block Diagram............................................................................................ 31
11 EMAC Module Block Diagram ........................................................................................... 35
12 EMAC Control Module Revision ID Register (REVID)................................................................ 57
13 EMAC Control Module Software Reset Register (SOFTRESET) ................................................... 58
14 EMAC Control Module Interrupt Control Register (INTCONTROL)................................................. 59
15 EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register
(CnRXTHRESHEN) ....................................................................................................... 60
16 EMAC Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (CnRXEN)....................... 61
17 EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (CnTXEN) ...................... 62
18 EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (CnMISCEN) ............ 63
19 EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register
(CnRXTHRESHSTAT).................................................................................................... 64
20 EMAC Control Module Interrupt Core 0-2 Receive Interrupt Status Register (CnRXSTAT) .................... 65
21 EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (CnTXSTAT).................... 66
22 EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (CnMISCSTAT) .......... 67
23 EMAC Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (CnRXIMAX)......... 68
24 EMAC Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (CnTXIMAX) ........ 69
25 MDIO Revision ID Register (REVID).................................................................................... 70
26 MDIO Control Register (CONTROL).................................................................................... 71
27 PHY Acknowledge Status Register (ALIVE) ........................................................................... 72
28 PHY Link Status Register (LINK)........................................................................................ 72
29 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ....................................... 73
30 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) ..................................... 74
31 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW).............................. 75
32 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) ............................ 76
33 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)........................... 77
34 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) .................... 78
35 MDIO User Access Register 0 (USERACCESS0) .................................................................... 79
36 MDIO User PHY Select Register 0 (USERPHYSEL0) ............................................................... 80
37 MDIO User Access Register 1 (USERACCESS1) .................................................................... 81
38 MDIO User PHY Select Register 1 (USERPHYSEL1) ............................................................... 82
39 Transmit Revision ID Register (TXREVID)............................................................................. 86
40 Transmit Control Register (TXCONTROL)............................................................................. 86
41 Transmit Teardown Register (TXTEARDOWN) ....................................................................... 87
42 Receive Revision ID Register (RXREVID) ............................................................................. 88
43 Receive Control Register (RXCONTROL) ............................................................................. 88
44 Receive Teardown Register (RXTEARDOWN) ....................................................................... 89
45 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) ............................................... 90
46 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED).............................................. 91
6
List of Figures SPRUFL5B–April 2011
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