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Architecture
2.15 Initialization
2.15.1 Enabling the EMAC/MDIO Peripheral
When the device is powered on, the EMAC peripheral may be in a disabled state. Before any EMAC
specific initialization can take place, the EMAC needs to be enabled; otherwise, its registers cannot be
written and the reads will all return a value of zero.
The EMAC/MDIO is enabled through the Power and Sleep Controller (PSC) registers. For information on
how to enable the EMAC peripheral from the PSC, see your device-specific System Reference Guide.
When first enabled, the EMAC peripheral registers are set to their default values. After enabling the
peripheral, you may proceed with the module specific initialization.
2.15.2 EMAC Control Module Initialization
The EMAC control module is used for global interrupt enables and to pace interrupts using 1ms time
windows. There is also an 8K block of CPPI RAM local to the EMAC that is used to hold packet buffer
descriptors.
Note that although the EMAC control module and the EMAC module have slightly different functions, in
practice, the type of maintenance performed on the EMAC control module is more commonly conducted
from the EMAC module software (as opposed to the MDIO module).
The initialization of the EMAC control module consists of two parts:
1. Configuration of the interrupt to the CPU.
2. Initialization of the EMAC control module:
• Setting the interrupt pace counts using the EMAC control module registers INTCONTROL,
CnRXIMAX, and CnTXIMAX
• Initializing the EMAC and MDIO modules
• Enabling interrupts in the EMAC control module using the EMAC control module interrupt control
registers CnRXTHRESHEN, CnRXEN, CnTXEN, and CnMISCEN.
The process of mapping the EMAC interrupts to the CPU is done through the CPU interrupt controller.
Once the interrupt is mapped to a CPU interrupt, general masking and unmasking of interrupts (to control
reentrancy) should be done at the chip level by manipulating the interrupt core enable mask registers.
2.15.3 MDIO Module Initialization
The MDIO module is used to initially configure and monitor one or more external PHY devices. Other than
initializing the software state machine (details on this state machine can be found in the IEEE 802.3
standard), all that needs to be done for the MDIO module is to enable the MDIO engine and to configure
the clock divider. To set the clock divider, supply an MDIO clock of 1 MHz. For example, if the peripheral
clock is 50 MHz, the divider can be set to 50.
Both the state machine enable and the MDIO clock divider are controlled through the MDIO control
register (CONTROL). If none of the potentially connected PHYs require the access preamble, the
PREAMBLE bit in CONTROL can also be set to speed up PHY register access.
If the MDIO module is to operate on an interrupt basis, the interrupts can be enabled at this time using the
MDIO user command complete interrupt mask set register (USERINTMASKSET) for register access and
the MDIO user PHY select register (USERPHYSELn) if a target PHY is already known.
Once the MDIO state machine has been initialized and enabled, it starts polling all 32 PHY addresses on
the MDIO bus, looking for an active PHY. Since it can take up to 50 μs to read one register, it can be
some time before the MDIO module provides an accurate representation of whether a PHY is available.
Also, a PHY can take up to 3 seconds to negotiate a link. Thus, it is advisable to run the MDIO software
off a time-based event rather than polling.
For more information on PHY control registers, see your PHY device documentation.
49
SPRUFL5B–April 2011 EMAC/MDIO Module
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