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158 Software Developer’s Manual
Ethernet Interface
8.2.3 MII – 10/100 Mb/s
The internal MII implementation for the Ethernet controller provides full IEEE 802.3 and IEEE
802.3u compliant operation for 10Mb/s and 100Mb/s operation in conjunction with the onboard
MII compliant PHY.
The MII uses a clocked, nibble-wide (4-bit) data path in each direction. The clock rate for Fast
Ethernet operation is 25 MHz with data transfer speed of 4 bits x 25 MHz = 100 Mb/s. For
10 Mb/s operation the clock rate is 2.5 MHz and also uses the nibble-wide data path.
8.3 Internal Interface
1
The Ethernet controller supports the IEEE 802.3 MII Management Interface also known as the
Management Data Input/Output (MDI/O) Interface. This interface allows upper-layer devices to
monitor and control the state of the PHY.
For the
82546GB/EB, 82545GM/EM, 82541xx, 82540EP/EM, and 82547GI/EI, the MDI/O
interface consists of an internal connection, a special protocol that runs across the connection, and
an internal set of addressable registers. For the
82541xx and 82547GI/EI, the physical interface
between the MAC and PHY is not available externally.
For the
82544GC/EI, the MDI/O interface consists of a physical connection, a special protocol that
runs across the connection, and an internal set of addressable registers. The physical interface
consists of a (B_MDIO) data line and a clock line (O_MDC).
• O_MDC:
Management Data Clock, used by the PHY as a clock timing reference for information transfer
on the B_MDI/O signal. The O_MDC is not a continuous signal and can be frozen by the
Ethernet controller when no management data is transferred. The O_MDC signal has a
maximum operating frequency of 2.5 MHz.
• B_MDO:
Management Data I/O, a bidirectional data signal used to transfer control information and
status between the Ethernet controller and the PHY (read and write PHY management
registers). The B_MDO signal is sampled by the rising edge of the O_MDC signal.
Software can use MDI/O to read and write registers in a internal PHY by accessing the Ethernet
controller’s MDIC register.
8.4 Duplex Operation
The 82546GB/EB and 82545GM/EM supports half-duplex and full-duplex 10/100 Mb/s mode.
Half-duplex in 1000 Mb/s mode using either the Internal SerDes or GMII interface is NOT
supported.
The
82544GC/EI, 82540EP/EM, 82541xx, and 82547GI/EI, support half-duplex and full-duplex
10/100 Mb/s mode or 1000 MB/s mode. However, only full-duplex mode is supported when the
82544GC/EI TBI interface option is used.
1. MDIO/MDC Interface for the 82544GC/EI, 82540EP/EM, 82541xx, and 82547GI/EI.