Filter
Top Products
Receive and Transmit Description
26 Software Developer’s Manual
3.2.5 Receive Descriptor Write-Back
Processors have cache line sizes that are larger than the receive descriptor size (16 bytes).
Consequently, writing back descriptor information for each received packet would cause expensive
partial cache line updates. Two mechanisms minimize the occurrence of partial line write backs:
• Receive descriptor packing
• Null descriptor padding
The following sections explain these mechanisms.
3.2.5.1 Receive Descriptor Packing
To maximize memory efficiency, receive descriptors are “packed” together and written as a cache
line whenever possible. Descriptors accumulate and are written out in one of three conditions:
• RXDCTL.WTHRESH descriptors have been used (the specified max threshold of unwritten
used descriptors has been reached)
• The receive timer expires (RADV or RDTR)
• Explicit software flush (RDTR.FPD)
For the first condition, if the number of descriptors specified by RXDCTL.WTHRESH are used,
they are written back, regardless of cacheline alignment. It is therefore recommended that
WTHRESH be a multiple of cacheline sizes.
In the second condition, a timer (RDTR or RADV) expiration causes all used descriptors to be
written back prior to initiating an interrupt.
In the second condition for the 82544GC/EI, a timer (RDTR) is included to force timely write–
back of descriptors. The first packet after timer initialization starts the timer. Timer expiration
flushes any accumulated descriptors and sets an interrupt event (receiver timer interrupt). In
general, the arrival rate is sufficiently fast enough that packing is the common case under load.
For the final condition, software may explicitly flush accumulated descriptors by writing the timer
register with the high order bit set.
3.2.5.2 Null Descriptor Padding
Hardware stores no data in descriptors with a null data address. Software can make use of this
property to cause the first condition under receive descriptor packing to occur early. Hardware
writes back null descriptors with the DD bit set in the status byte and all other bits unchanged.
3.2.6 Receive Descriptor Queue Structure
Figure 3-2 shows the structure of the receive descriptor ring. Hardware maintains a circular ring of
descriptors and writes back used descriptors just prior to advancing the head pointer. Head and tail
pointers wrap back to base when “size” descriptors have been processed.
Software adds receive descriptors by writing the tail pointer with the index of the entry beyond the
last valid descriptor. As packets arrive, they are stored in memory and the head pointer is
incremented by hardware. When the head pointer is equal to the tail pointer, the ring is empty.
Hardware stops storing packets in system memory until software advances the tail pointer, making
more receive buffers available.