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Receive and Transmit Description
28 Software Developer’s Manual
• Receive Descriptor Tail register (RDT)
This register holds a value that is an offset from the base, and identifies the location beyond the
last descriptor hardware can process. Note that tail should still point to an area in the descriptor
ring (somewhere between RDBA and RDBA + RDLEN). This is because tail points to the
location where software writes the first new descriptor.
If software statically allocates buffers, and uses memory read to check for completed descriptors, it
simply has to zero the status byte in the descriptor to make it ready for reuse by hardware. This is
not a hardware requirement (moving the hardware tail pointer is), but is necessary for performing
an in–memory scan.
3.2.7 Receive Interrupts
The Ethernet controller can generate four receive-related interrupts:
• Receiver Timer Interrupt (ICR.RXT0)
• Small Receive Packet Detect (ICR.SRPD)
• Receive Descriptor Minimum Threshold (ICR.RXDMT0)
• Receiver FIFO Overrun (ICR.RX0)
3.2.7.1 Receive Timer Interrupt
The Receive Timer Interrupt is used to signal most packet reception events (the Small Receive
Packet Detect interrupt is also used in some cases as described later in this section). In order to
minimize the interrupts per work accomplished, the Ethernet controller provides two timers to
control how often interrupts are generated.
3.2.7.1.1 Receive Interrupt Delay Timer / Packet Timer (RDTR)
The Packet Timer minimizes the number of interrupts generated when many packets are received
in a short period of time. The packet timer is started once a packet is received and transferred to
host memory (specifically, after the last packet data byte is written to memory) and is reinitialized
(to the value defined in RDTR) and started EACH TIME a new packet is received and transferred
to the host memory. When the Packet Timer expires (e.g. no new packets have been received and
transferred to host memory for the amount of time defined in RDTR) the Receive Timer Interrupt is
generated.
Setting the Packet Timer to 0b disables both the Packet Timer and the Absolute Timer (described
below) and causes the Receive Timer Interrupt to be generated whenever a new packet has been
stored in memory.
Writing to RDTR with its high order bit (FPD) set forces an explicit writeback of consumed
descriptors (potentially a partial cache lines amount of descriptors), causes an immediate expiration
of the Packet Timer and generates a Receive Timer Interrupt.
The Packet Timer is reinitialized (but not started) when the Receive Timer Interrupt is generated
due to an Absolute timer expiration or Small Receive Packet Detect Interrupt.
See section Section 13.4.30 for more details on the Packet Timer.