Filter
Top Products
Software Developer’s Manual 19
Receive and Transmit Description
Receive and Transmit Description 3
3.1 Introduction
This section describes the packet reception, packet transmission, transmit descriptor ring structure,
TCP segmentation, and transmit checksum offloading for the PCI/PCI-X Family of Gigabit
Ethernet Controllers.
Note: The 82544GC/EI does not support IPv6.
3.2 Packet Reception
In the general case, packet reception consists of recognizing the presence of a packet on the wire,
performing address filtering, storing the packet in the receive data FIFO, transferring the data to a
receive buffer in host memory, and updating the state of a receive descriptor.
3.2.1 Packet Address Filtering
Hardware stores incoming packets in host memory subject to the following filter modes. If there is
insufficient space in the receive FIFO, hardware drops them and indicates the missed packet in the
appropriate statistics registers.
The following filter modes are supported:
• Exact Unicast/Multicast — The destination address must exactly match one of 16 stored
addresses. These addresses can be unicast or multicast.
• Promiscuous Unicast — Receive all unicasts.
• Multicast — The upper bits of the incoming packet’s destination address index a bit vector
that indicates whether to accept the packet; if the bit in the vector is one, accept the packet,
otherwise, reject it. The controller provides a 4096 bit vector. Software provides four choices
of which bits are used for indexing. These are [47:36], [46:35], [45:34], or [43:32] of the
internally stored representation of the destination address.
• Promiscuous Multicast — Receive all multicast packets.
• VLAN — Receive all VLAN
1
packets that are for this station and have the appropriate bit set
in the VLAN filter table. A detailed discussion and explanation of VLAN packet filtering is
contained in Section 9.3.
Normally, only good packets are received. These are defined as those packets with no CRC error,
symbol error, sequence error, length error, alignment error, or where carrier extension or receive
errors are detected. However, if the store–bad–packet bit is set in the Device Control register
(RCTL.SBP), then bad packets that pass the filter function are stored in host memory. Packet errors
are indicated by error bits in the receive descriptor (RDESC.ERRORS). It is possible to receive all
packets, regardless of whether they are bad, by setting the promiscuous enables (RCTL.UPE/MPE)
and the store–bad–packet bit (RCTL.SBP).
1. Not applicable to the 82541ER.