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Software Developer’s Manual 327
Register Descriptions
13.5 Filter Registers
This section contains detailed descriptions for those registers associated with the Ethernet
controller’s address filter capabilities.
13.5.1 Multicast Table Array
MTA[127:0] (05200h-053FCh; R/W)
The multicast table array is a way to extend address filtering beyond the 16 perfect in the Receive
Address Register (RAR). Note that the MTA is an imperfect
filter that allows you to filter on 4096
similar addresses using a much smaller data structure than would be required to store all 4096
addresses in a linear table such as a perfect filter.
The Ethernet controller provides a 4096-bit vector multicast table array that is used when all the 16
perfect filters in the Receive Address Registers (RAR) are used. There is one register per 32 bits of
the Multicast Address Table for a total of 128 registers (thus the MTA[127:0] designation). The
size of the word array depends on the number of bits implemented in the multicast address table.
Software must mask to the desired bit on reads and supply a 32-bit word on writes. Accesses to this
table must be 32-bit.
The operating system provides a list of addresses that it would like to respond to. The driver fills in
the Receive Address Registers (RAR) first, as these are exact matching addresses. If the OS
provides more than the 16 addresses available in RARs, the overflow is put into the MTA. The
MTA does not match the exact address, but a subset of the address. Each address filtered on is
represented by a single bit within the MTA table. Software needs to do the same calculations that
hardware does when checking against the MTA, so it can program the appropriate bit in the MTA.
When the hardware receives an address, it goes through the RARs, and if it does not find a match,
it does the same calculations that are described below on the address that it was given and only
checks one bit in the MTA. If that bit is set, it allows the packet to pass. If that bit is not set, it drops
the packet.
The calculation to find that bit is as follows (using the example of 12:34:56:78:9A:BCh):
Check the RCTL bits 13:12 to see what they are set to. In this example it is 00h that means that
we only look at bits 47:36. This corresponds to 0BC9h in the example address (assuming that
in your example 12 is the least significant byte and 0BCh is the most significant byte). The
way the address is stored in memory is the same that it would be going out on the wire, which
is the least significant byte is the first on the wire, so it looks like this:
BC:9A:78:56:34:12h so that the LSB (12) goes on the wire first. Breaking 0BC9h down into a
word:
0BC9h = 0000_1011_1100_1001b
Table 13-89. MTA Register Bit Description
Field Bit(s)
Initial
Value
Description
MC Bit Vector 31:0 X
Multicast bit vector specifying 32 bits in the multicast address filter
table.