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390 Software Developer’s Manual
Diagnostics and Testability
15.1.3.1 Internal Loopback
This loopback mode internally loops back the transmit to receive path in the PHY, exercising the
internal GMII/MII bus. Programming both MAC and PHY is required. Following is the flow:
/* Auto-MDI/MDIX Off */
e1000_write_phy_reg(16, 0x0808);
/* reset to update Auto-MDI/MDIX */
e1000_write_phy_reg(0, 0x9140);
/* autoneg off */
e1000_write_phy_reg(0, 0x8140);
/* force 1000, set loopback */
e1000_write_phy_reg(0, 0x4140);
/* Now set up the MAC to the same speed/duplex as the PHY. */
ctrl_reg = E1000_READ_REG(CTRL);
ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
E1000_CTRL_FRCDPLX | /* Set the Force Duplex Bit */
E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */
E1000_CTRL_FD); /* Force Duplex to FULL */
/* Set the ILOS bit on the fiber Nic is half duplex link is detected. */
stat_reg = E1000_READ_REG(STATUS);
if((stat_reg & E1000_STATUS_FD) = 0)
ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
E1000_WRITE_REG(CTRL, ctrl_reg);
15.2 Testability
The Ethernet controller uses full Boundary Scan/IEEE 1149.1 JTAG standard test methods. The
TAP controller supports EXTEST, SAMPLE/PRELOAD, IDCODE, USERCODE, and BYPASS
instructions.