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Software Developer’s Manual 331
Register Descriptions
Table 13-92. VFTA[127:0] Bit Description
13.6 Wakeup Registers
13.6.1 Wakeup Control Register
WUC (05800h; R/W)
This register is reset any time LAN_PWR_GOOD is set to 0b. When AUX_POWER equals 0b,
this register is also reset by de-asserting (rising edge) RST#.
31 0
VLAN Filter Bit Vector
Field Bit(s)
Initial
Value
Description
Bit Vector 31:0 X
Double-word wide bit vector specifying 32 bits in the VLAN
Filter table.
31 43210
Reserved APMPME PME_S PME_EN APME
Field Bit(s)
Initial
Value
Description
APME 0 0b
Advance Power Management Enable
If set to 1b, APM Wakeup is enabled.
Note: Always 0b for the 82541ER.
PME_En 1 0b
PME_En
This read/write bit is used by the driver to access the PME_En
bit of the Power Management Control / Status Register
(PMCSR) without writing to the PCI configuration space.
Note: Do not set this bit for the 82541ER.
PME_Status 2 0b
PME_Status
This bit is set when the Ethernet controller
receives a wakeup
event. It is the same as the PME_Status bit in the Power
Management Control / Status Register (PMCSR). Writing a 1b
to this bit clears the PME_Status bit in the PMCSR.