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Software Developer’s Manual 341
Register Descriptions
All Statistics registers reset when read. 64-bit registers reset whenever the upper 32 bits are read. In
addition, they stick at FFFFh_FFFFh when the maximum value is reached.
The Statistics registers are not hardware initialized. Their default value is unknown. Software
should read the contents of all registers in order to clear them prior to enabling the receive and
transmit channels.
Note: For the receive statistics, it should be noted that a packet is indicated as “received” if it passes the
device filters, and it is placed in the packet buffer memory. A packet does not have to be transferred
to host memory in order to be counted as “received.”
13.7.1 CRC Error Count
CRCERRS (04000h; R)
Counts the number of receive packets with CRC errors. In order for a packet to be counted in this
register, it must pass address filtering and must be 64 bytes or greater (from <Destination Address>
through <CRC>, inclusively) in length. If receives are not enabled, then this register does not
increment.
Table 13-93. CRCERRS Register Bit Description
13.7.2 Alignment Error Count
ALGNERRC (04004h; R)
Counts the number of receive packets with alignment errors (the packet is not an integer number of
bytes in length). In order for a packet to be counted in this register, it must pass address filtering
and must be 64 bytes or greater (from <Destination Address> through <CRC>, inclusively) in
length. If receives are not enabled, then this register does not increment. This register is valid only
in MII mode during 10/100 Mb/s operation.
31 0
CEC
Field Bit(s)
Initial
Value
Description
CEC 31:0 0b CRC error count