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386 Software Developer’s Manual
General Initialization and Reset Operation
RST#:
When asserted, all PCI signals are forced to a high impedance state. Upon deassertion, the Ethernet
controller’s internal registers, excluding the following exceptions, are reset.
General Registers: Reset to power-on values.
Interrupt Registers: Reset to power-on values.
Receive Registers: Reset to power-on values (exceptions are the RAH/RAL, MTA,
VFTA and RDBAH/RDBAL registers, which are not reset to any
preset value. The valid bit of the RAH register is cleared).
Transmit Registers: Reset to power-on values (exceptions are the TDBAH/TDBAL,
and TIPG registers, which is not reset to any preset value).
Statistics Registers: Reset to power-on values.
Wakeup Registers: The WUC (except for the
PME_En and PME_Status bits if
AUX_POWER = 1b), WUFC, IPAV, and FFLT registers are reset
to their default value.
Diagnostic Registers: Reset to power-on values (exception is the PBM memory, which is
not reset to any preset value).
PCI Config Space: Context Lost; requires initialization. If AUX_POWER = 1b then
the
PME_En and PME_Status bits of the Power Management
Control/Status Register are preserved.
PHY: RST# is asserted for 400 ns after deassertion of RST#.
Asserting RST# puts the Ethernet controller into the “Dr” Power Management state. See Section
6.3.1.1 for details on the power states, and Section 6.3.2.4 for reset related timing.
Deasserting RST# also causes the EEPROM to be re-read and the registers that get values from the
EEPROM to be re-loaded.
Global Reset:
Bit 26 of the Device Control Register (CTRL.RST) performs an Ethernet controller reset of all
functions to their equivalent power on state similar to asserting RST#, except that the state of the
PCI core and PCI configuration space is not affected.
General Registers: Reset to power-on values.
Interrupt Registers: Reset to power-on values.
Receive Registers: Reset to power-on values (exceptions are the RAH/RAL, MTA, VFTA
and RDBAH/RDBAL registers, which are not reset to any preset
value. The valid bit of the RAH register is cleared).
Transmit Registers: Reset to power-on values (exceptions are the TDBAH/TDBAL, and
TIPG registers).
Statistics Registers: Reset to power-on values.
Wakeup Registers: The WUC (except for the
PME_En and PME_Status bits), WUFC,
IPAV, and FFLT registers are reset to their default value.
Diagnostic Registers: Reset to power-on values (exception is the PBM memory, which is not
reset to any preset value).
PCI Config Space: No Change.
PHY: No effect.