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Datasheet
7
Networkin
g
Silicon —GD82559ER
3. Si
g
nal Descri
p
tions
3.1 Si
g
nal T
yp
e Definitions
3.2 PCI Bus Interface Si
g
nals
3.2.1 Address and Data Si
g
nals
Type Name Description
IN Input The input pin is a standard input onl
y
si
g
nal.
OUT Output
The output pin is a Totem Pole Output pin and is a standard
active driver.
T/S Tri-State The tri-state pin is a bidirectional, input/output pin.
S/T/S Sustained Tri-State
The sustained tri-state pin is an active low tri-state si
g
nal owned
and driven b
y
one a
g
ent at a time. The a
g
ent assertin
g
the S/T/
S pin low must drive it hi
g
h at least one clock c
y
cle before
floatin
g
the pin. A new a
g
ent can onl
y
assert an S/T/S si
g
nal low
one clock c
y
cle after it has been tri-stated b
y
the previous
owner.
O/D Open Drain
The open drain pin allows multiple devices to share this si
g
nal
as a wired-OR.
A/I Analo
g
Input The analo
g
input pin is used for analo
g
input si
g
nals.
A/O Analo
g
Output The analo
g
output pin is used for analo
g
output si
g
nals.
B Bias The bias pin is an input bias.
Symbol Type Name and Function
AD[31:0] T/S
Address and Data.
The address and data lines are multiplexed on
the same PCI pins. A bus transaction consists of an address phase
followed b
y
one or more data phases. Durin
g
the address phase, the
address and data lines contain the 32-bit ph
y
sical address. For I/O,
this is a b
y
te address; for confi
g
uration and memor
y
, it is a Dword
address. The 82559ER uses little-endian b
y
te orderin
g
(
in other
words, AD[31:24] contain the most si
g
nificant b
y
te and AD[7:0]
contain the least si
g
nificant b
y
te
)
. Durin
g
the data phases, the address
and data lines contain data.
C/BE[3:0]# T/S
Command and Byte Enable.
The bus command and b
y
te enable
si
g
nals are multiplexed on the same PCI pins. Durin
g
the address
phase, the C/BE# lines define the bus command. Durin
g
the data
phase, the C/BE# lines are used as B
y
te Enables. The B
y
te Enables
are valid for the entire data phase and determine which b
y
te lanes
carr
y
meanin
g
ful data.
PAR T/S
Parity.
Parit
y
is even across AD[31:0] and C/BE[3:0]# lines. It is stable
and valid one clock after the address phase. For data phases, PAR is
stable and valid one clock after either IRDY# is asserted on a write
transaction or TRDY# is asserted on a read transaction.Once PAR is
valid, it remains valid until one clock after the completion of the current
data phase. The master drives PAR for address and write data
phases; and the tar
g
et, for read data phases.