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Networking Silicon — GD82559ER
10.4 Timing Specifications
10.4.1 Clocks Specifications
10.4.1.1 PCI Clock Specifications
The 82559ER uses the PCI Clock signal directly. Figure 26 shows the clock waveform and required
measurement points for the PCI Clock signal. Table 22 summarizes the PCI Clock specifications.
NOTES:
1. The 82559ER will work with any PCI clock frequency up to 33 MHz.
2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate is met across the
minimum peak-to-peak portion of the clock waveform as shown in Figure 26.
10.4.1.2 X1 Specifications
X1 serves as a signal input from an external crystal or oscillator. Table 23 defines the 82559ER
requirements from this signal.
Figure 26. PCI Clock Waveform
0.6V
CC
0.475V
CC
0.4V
CC
0.325V
CC
0.2V
CC
0.4V
CC
p
-to-
p
(
minimum
)
T_hi
g
h T_low
T_c
y
c
Table 22. PCI Clock Specifications
Symbol Parameter Min Max Units Notes
T1 T
cyc
CLK Cycle Time 30 ns 1
T2 T
high
CLK High Time 11 ns
T3 T
low
CLK Low Time 11 ns
T4 T
slew
CLK Slew Rate 1 4 V/ns 2
Table 23. X1 Clock Specifications
Symbol Parameter Min Typical Max Units Notes
T8 Tx1_dc X1 Duty Cycle 40% 60%
T9 Tx1_pr X1 Period 40 ns ±50PPM