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GD82559ER — Networkin
g
Silicon
50
Datasheet
7.1.4 PCI Revision ID Re
g
ister
The Revision ID is an 8-bit read only register with a default value of 08h for the 82559ER. The
three least significant bits of the Revision ID can be overridden by the ID and Revision ID fields in
the EEPROM (Section 4.4, “Serial EEPROM Interface” on page 28).
7.1.5 PCI Class Code Re
g
ister
The Class Code register is read only and is used to identify the generic function of the device and,
in some cases, specific register level programming interface. The register is broken into three byte
size fields. The upper byte is a base class code and specifies the 82559ER as a network controller,
2H. The middle byte is a subclass code and specifies the 82559ER as an Ethernet controller, 0H.
The lower byte identifies a specific register level programming interface and the 82559ER always
returns a 0h in this field.
7.1.6 PCI Cache Line Size Re
g
ister
In order for the 82559ER to support the Memory Write and Invalidate (MWI) command, the
82559ER must also support the Cache Line Size (CLS) register in PCI Configuration space. The
register supports only cache line sizes of 8 and 16 Dwords. Any value other than 8 or 16 that is
written to the register is ignored and the 82559ER does not use the MWI command. If a value other
than 8 or 16 is written into the CLS register, the 82559ER returns all zeroes when the CLS register
is read. The figure below illustrates the format of this register.
24 Parit
y
Error Detected
This bit indicates whether a parit
y
error has been detected. This bit is set to
1b when the followin
g
three conditions are met:
1. The bus a
g
ent asserted PERR# itself or observed PERR# asserted.
2. The a
g
ent settin
g
the bit acted as the bus master for the operation in
which the error occurred.
3. The Parit
y
Error Response bit in the command re
g
ister
(
bit 6
)
is set.
In the 82559ER, the initial value of the Parit
y
Error Detected bit is 0b. This
bit is set until cleared b
y
writin
g
a 1b.
23 Fast Back-to-Back
This bit indicates a device’s abilit
y
to accept fast back-to-back transactions
when the transactions are not to the same a
g
ent. A value of 0b disables
fast back-to-back abilit
y
. A value of 1b enables fast back-to-back abilit
y
. In
the 82559ER, this bit is read onl
y
and is set to 1b.
20 Capabilities List
This bit indicates whether the 82559ER implements a list of new
capabilities such as PCI Power Mana
g
ement. A value of 0b means that this
function does not implement the Capabilities List. If this bit is set to 1b, the
Cap_Ptr re
g
ister provides an offset into the 82559ER PCI Confi
g
uration
space pointin
g
to the location of the first item in the Capabilities List. This
bit is set onl
y
if the power mana
g
ement bit in the EEPROM is set.
19:16 Reserved These bits are reserved and should be set to 0000b.
Table 6. PCI Status Re
g
ister Bits
Bits Name Description
76543210
000RWRW000
Fi
g
ure 20. Cache Line Size Re
g
ister