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GD82559ER — Networkin
g
Silicon
32
Datasheet
4.6 Media Inde
p
endent Interface
(
MII
)
Mana
g
ement Interface
The MII management interface allows the CPU to control the PHY unit via a control register in the
82559ER. This allows the software driver to place the PHY in specific modes such as full duplex,
loopback, power down, etc., without the need for specific hardware pins to select the desired mode.
This structure allows the 82559ER to query the PHY unit for status of the link. This register is the
MDI Control Register and resides at offset 10h in the 82559ER CSR. (The MDI registers are
described in detail in Section 9., “PHY Unit Registers” on page 65.) The CPU writes commands to
this register and the 82559ER reads or writes the control/status parameters to the PHY unit through
the MDI register. Although the 82559ER follows the MII format, the MI bus is not accessible on
external pins.