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IntelP®P Server Board S3420GP TPS Design and Environmental Specifications
9.4.1 Grounding
The grounds of the power supply output connector pins provide the power return path. The
output connector ground pins are connected to the safety ground (power supply enclosure).
This grounding is designed to ensure passing the maximum allowed common mode noise levels.
The power supply is provided with a reliable protective earth ground. All secondary circuits are
connected to protective earth ground. Resistance of the ground returns to chassis does not
exceed 1.0 mΩ. This path may be used to carry DC current.
9.4.2 Standby Outputs
The 5 VSB output is present when an AC input greater than the power supply turn on voltage is
applied.
9.4.3 Remote Sense
The power supply has remote sense return (ReturnS) to regulate out ground drops for all output
voltages: +3.3 V, +5 V, +12 V, -12 V, and 5 VSB. The power supply uses remote sense to
regulate out drops in the system for the +3.3 V, +5 V, and 12 V outputs. The power supply must
operate within specification over the full range of voltage drops from the power supply’s output
connector to the remote sense points.
9.4.4 Voltage Regulation
The power supply output voltages must stay within the following voltage limits when operating at
steady state and dynamic loading conditions. These limits include the peak-peak ripple/noise.
All outputs are measured with reference to the return remote sense signal (ReturnS).
Table 58. Voltage Regulation Limits
Parameter Tolerance Minimum Normal Maximum Units
+ 3.3 V - 5% / +5% +3.14 +3.30 +3.46 Vrms
+ 5 V - 5% / +5% +4.75 +5.00 +5.25 Vrms
+ 12 V - 5% / +5% +11.40 +12.00 +12.60 Vrms
- 12 V - 10% / +10% -13.20 -12.00 -10.80 Vrms
+ 5 VSB - 5% / +5% +4.75 +5.00 +5.25 Vrms
9.4.5 Dynamic Loading
The output voltages remain within limits for the step loading and capacitive loading specified in
the following table. The load transient repetition rate is tested between 50 Hz and 5 kHz at duty
cycles ranging from 10%-90%. The load transient repetition rate is only a test specification. The
∆ step load may occur anywhere within the Min load to the Max load conditions.
Table 59. Transient Load Requirements
Output
∆ Step Load Size
(See note 2)
Load Slew Rate Test capacitive Load
+3.3 V 5.0 A
0.25 A/µsec 250 µF
+5 V 6.0 A
0.25 A/µsec 400 µF
12 V 11.0 A
0.25 A/µsec 500 µF
Revision 1.0
Intel order number E65697-003
89