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Design and Environmental Specifications IntelP®P Server Board S3420GP TPS
+5 VSB 0.5 A
0.25 A/µsec 20 µF
Notes:
1.
Step loads on each 12 V output may happen simultaneously and should be tested that way.
9.4.6 Capacitive Loading
The power supply is stable and meets all requirements with the following capacitive loading
ranges.
Table 60. Capacitve Loading Conditions
Output Minimum Maximum Units
+3.3 V 100 2200
µF
+5 V 400 2200
µF
+12 V 500 2200
µF
-12 V 1 350
µF
+5 VSB 20 350
µF
9.4.7 Closed-loop Stability
The power supply is unconditionally stable under all line/load/transient load conditions including
capacitive load ranges. A minimum of 45° phase margin and -10 dB-gain margin is required.
The power supply manufacturer provides proof of the unit’s closed-loop stability with local
sensing through the submission of Bode plots. Closed-loop stability is ensured at the maximum
and minimum loads as applicable.
9.4.8 Common Mode Noise
The Common Mode noise on any output does not exceed 350 mV pk-pk over the frequency
band of 10 Hz to 20 MHz.
The measurement is made across a 100Ω resistor between each of the DC outputs,
including ground, at the DC power connector and chassis ground (power subsystem
enclosure).
The test setup uses a FET probe such as Tektronix* model P6046 or equivalent.
9.4.9 Ripple / Noise
The maximum allowed ripple/noise output of the power supply is defined in the following table.
This is measured over a bandwidth of 0 Hz to 20 MHz at the power supply output connectors. A
10 µF tantalum capacitor is placed in parallel with a 0.1 µF ceramic capacitor at the point of
measurement.
Table 61. Ripple and Noise
+3.3 V +5 V +12 V -12 V +5 VSB
50 mVp-p 50 mVp-p 120 mVp-p 120 mVp-p 50 mVp-p
9.4.10 Timing Requirements
The timing requirements for the power supply operation are as follows:
Revision 1.0
Intel order number E65697-003
90