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IntelP®P Server Board S3420GP TPS Functional Architecture
Memory BIST, the system acts as if no memory is available, beeping and halting with
itialization process is unable to
properly perform the DQ/DQS training on a memory channel, the BIOS emits a beep
code and displays POST Diagnostic LED code 0xEA momentarily during the beeping. If
an two quad-ranked DIMMs are installed on any
3.2.
emory of the system during POST if Quiet Boot is
the total size of memory discovered by the BIOS
individual sizes of installed DDR3 DIMMs in the
ective Memory of the system in the BIOS Setup. The term
Effective Memory refers to the total size of all active DDR3 DIMMs (not disabled) and not
tic
sor, and memory-mapped I/O regions. This region appears as a
system, the operating system reclaims all these reserved
tion space. This is based on the selection of
Maximize Memory below 4 GB in the BIOS Setup.
sage of memory below 4 GB for an operating
e
the POST Diagnostic LED code 0xE8 (No Usable Memory) displayed.
z 0xEA - Channel Training Error: If the memory in
there is usable memory in the system on other channels, POST memory initialization
continues. Otherwise, the system halts with POST Diagnostic LED code 0xEA staying
displayed.
z 0xED - Population Error: If the installed memory contains a mix of RDIMMs and
UDIMMs, the system halts with POST Diagnostic LED code 0xED.
z 0xEE - Mismatch Error: If more th
channel in the system, the system halts with POST Diagnostic LED code 0xEE.
3 Publishing System Memory
• The BIOS displays the Total M
disabled in the BIOS setup. This is
during POST, and is the sum of the
system.
• The BIOS displays the Eff
used as redundant units.
• The BIOS provides the total memory of the system in the main page of the BIOS setup.
This total is the same as the amount described by the first bullet in this section.
• If Quiet Boot is disabled, the BIOS displays the total system memory on the diagnos
screen at the end of POST. This total is the same as the amount described by the first
bullet in this section.
• The BIOS provides the total amount of memory in the system.
3.2.3.1 Memory Reservation for Memory-mapped Functions
A region of size 40 MB of memory below 4 GB is always reserved for mapping chipset,
proces BIOS (flash) spaces as
loss of memory to the operating system. In addition to this loss, the BIOS creates another
reserved region for memory-mapped PCIe functions, including a standard 64 MB or 256 MB of
standard PCI Express* MMIO configuration space.
If PAE is turned on in the operating
regions.
In addition to this memory reservation, the BIOS creates another reserved region for memory-
mapped PCI Express* functions, including a standard 64 MB or 256 MB of standard PCI
Express* Memory Mapped I/O (MMIO) configura
If this is set to Enabled, the BIOS maximizes u
system without PAE capability by limiting PCI Express* Extended Configuration Space to 64
buses rather than the standard 256 buses. This is done using the MAX_BUS_NUMBER featur
Revision 1.0
Intel order number E65697-003
17