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ThunderBird Avenger
TM
PCI Audio SAA7785
Accelerator
Philips Semiconductors Preliminary Specification
1999 Nov 12 19
SAA7785 SIGNAL DEFINITIONS
PCI LOCAL BUS INTERFACE SIGNALS
AD[31:0] PCI Address/Data
AD[31:0] contains a physical byte address during the first clock of a PCI transaction, and data
during subsequent clocks.
When the SAA7785 is a PCI master, AD[31:0] are outputs during the address phase of a trans-
action. They are either inputs or outputs during the data phase, depending on the type of PCI
cycle in process.
When the SAA7785 is a PCI slave, AD[31:0] are inputs during the address phase. They are
either inputs or outputs during the data phase, depending on the type of PCI cycle in process.
C/BE#[3:0] PCI Bus Command and Byte Enables
C/BE#[3:0] defines the bus command during the first clock of a PCI transaction, and the byte
enables during subsequent clocks.
C/BE#[3:0] are outputs when the SAA7785 is a PCI bus master and inputs when it is a PCI bus
slave.
DEVSEL# PCI Bus Device Select
When the SAA7785 is a PCI bus master the SAA7785 uses DEVSEL# to determine whether a
master abort should occur if DEVSEL# is not sampled active by clock 5 of the transaction, or to
determine whether a cycle is to be aborted or retried when a target-initiated termination occurs.
When the SAA7785 is a PCI bus slave, DEVSEL# is an output which the SAA7785 drives LOW
during the second PCLK after FRAME# assertion to the end of a transaction if the SAA7785 is
selected.
FRAME# PCI Bus Cycle Frame
When the SAA7785 is a PCI master, FRAME# is an output which indicates the beginning of a
SAA7785-initiated bus transaction. While FRAME# is asserted data transfers continue. When
FRAME# is deasserted the transaction is in the final data phase.
When the SAA7785 is a PCI slave, FRAME# is an input that initiates an I/O, memory or config-
uration register access if the SAA7785 is selected for the transaction. The SAA7785 latches the
C/BE#[3:0] and AD[31:0] signals on the PCLK edge on which it first samples FRAME# active.
IRDY# PCI Bus Initiator Ready
When the SAA7785 is a PCI master, IRDY# is an output which indicates the SAA7785’s ability
to complete the data phase of the current transaction. It is always asserted from the PCLK
cycle after FRAME# is asserted to the last clock of the transaction.
When the SAA7785 is a PCI slave, IRDY# is an input which causes the SAA7785 to hold-off
completion of a read or write cycle until sampled active.