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PCI Audio SAA7785
Accelerator
Philips Semiconductors Preliminary Specification
1999 Nov 12 21
GNT# PCI Bus Grant
An asserted GNT# pin indicates that the PCI master arbiter has granted bus ownership to the
SAA7785 chip.
INTA# PCI Bus Interrupt A
The interrupt output is a PCI compatible active low level sensitive interrupt. It is only used if the
SAA7785 is used in a non Common Architecture system. Otherwise it is tri-stated. It is driven
low when any of the internal interrupts are asserted.
PERR# PCI Bus Parity Error
This signal indicates a data parity error for any cycle type other than a Special Cycle command.
PERR# is made active two clocks after the completion of the data phase which caused the par-
ity error. This error signal may result in the generation of a non-maskable interrupt (NMI) or
other high priority interrupt sent to the CPU.
SERR# PCI Bus System Error
This signal indicates an address parity error, data parity errors on Special Cycle commands or
any other catastrophic system error. SERR# is an open-drain bidirectional pin which is driven
low for a single PCLK cycle by the agent reporting the error. This error may result in the gener-
ation of a non-maskable interrupt (NMI) or other high priority interrupt sent to the CPU.
IDSEL Initialization Device Select
IDSEL is used as a chip select during configuration register read and write operations. One
system board address line from AD[31:11] is used as IDSEL to select the SAA7785 configura-
tion space in the SAA7785 chip when used on the PCI bus.
CLKRUN# PCI Bus Clock Run Request
The SAA7785 uses CLKRUN# according to the Mobile PCI protocol to start the PCI clock or
keep the clock running whenever an internal PCI device requires it.
PCLK PCI Bus Clock Input
PCLK is the PCI bus clock input. It is used to synchronize all PCI bus operations and typically
runs at 33MHz.
RST# PCI Bus Reset
An active low version of the system reset, this signal causes the PCI interface to return to the
idle states in all state machines and asynchronously three-states all PCI bus signals. All regis-
ters will be reset to their default values as well. The CODEC interface line should be all driven
inactive along with the external memory interface. This reset will assert the DSP reset.
PME# PCI Bus Power Management Event
Reserved.