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PCI Audio SAA7785
Accelerator
Philips Semiconductors Preliminary Specification
1999 Nov 12 65
FIGURE 7 MULTIMEDIA TIMER BLOCK DIAGRAM
MULTIMEDIA TIMER REGISTER DEFINITION
There are five registers that control the multimedia timer. These registers are the timer control register, timer status, and
timer count registers. The timer control register resides in PCI configuration space. The remainder of the timer registers
are in I/O space.
MULTIMEDIA TIMER PCI CONFIGURATION REGISTERS
TABLE 69 TIMRCFG0 (RW/RO) - MULTIMEDIA TIMER CONFIG REGISTER 0
PCI CFG 0D7D6D5D4D3D2D1D0
Offset 64h RRRRRFSTCLKTMRRSTR
POR Value 00000000
Bit Name R/W Function
7:3 R RO Reserved. These bits return zeros.
PS BUS
CLOCK
DIVIDE
LOGIC
CTL
INTERNAL
PS BUS
INTERFACE
INTERRUPT
GENERATION
LOGIC
20 BIT - 1uS
RESOLUTION
UP COUNTER
CTL
COUNT
INTR
COUNTER CLOCK
CCLK