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ThunderBird Avenger
TM
PCI Audio SAA7785
Accelerator
Philips Semiconductors Preliminary Specification
1999 Nov 12 22
PCI GENERAL PURPOSE I/O
TEST INTERFACE/SERIAL CONFIGURATION PORT
GAME PORT INTERFACE
PGPIO[7:0] PCI General Purpose Input/Outputs
These eight pins are used as controls or data to devices external to the SAA7785 chip. Each
are independently controlled.
NAND#/CFG-
DAT
NAND Tree Test Enable/Serial Configuration Data
When this pin is pulled low and RST# is pulsed asserted, all output and I/O pins of the
SAA7785 will be forced into a three-state condition. Pulsed assertion of the RST# signal will
release the SAA7785 from this test mode.
If this pin is pulled high during PCI reset, then it is used to shift in PCI configuration data for the
Subsystem ID and the Subsystem Vendor ID in each of the PCI configuration headers present
in the SAA7785 chip. The Serial Configuration Port is a standard I
2
C interface. This line should
never be pulled low.
TRI#/CFGCLK Tri-State Test Enable/Serial Configuration Clock
When this pin is pulled low and RST# is pulsed asserted, the SAA7785 will enter the parametric
NAND tree test mode. The details of the NAND tree test mode are described later in this docu-
ment.
If this pin is pulled high during PCI reset, then this pin will supply the serial 400 KHz clock,
derived from OSC, to an external serial EEPROM. CFGCLK is used to synchronize the serial
configuration data.
JACX Joystick A X Axis
This pin functions as an input for the joystick A X-position axis.
JACY Joystick A Y Axis
This pin functions as an input for the joystick A Y-position axis.
JBCX Joystick B X Axis
This pin functions as an input for the joystick B X-position axis.
JBCY Joystick B Y Axis
This pin functions as an input for the joystick B Y-position axis.
JAB2 Joystick A Button 2 Interface
This pin functions as an input for the joystick A button 2.