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2.2 Interrupts
2-23
4513/4514 Group User’s Manual
Fig. 2.2.7 Timer 3 constant period interrupt setting example
g0 h
0
b3 b0
➀ Disable Interrupts
Timer 3 interrupt is temporarily disabled.
Interrupt enable flag INTE
Interrupt control register V2
“0”
✕✕✕
All interrupts disabled (DI instruction)
Timer 3 interrupt occurrence disabled
(TV2A instruction)
b3 b0
01
➁ Stop Timer 3 Operation
Timer 3 and prescaler are temporarily stopped.
Dividing ratio of prescaler is selected.
Timer control register W1
✕
Prescaler stop (TW1A instruction)
Prescaler divided by 16 selected
Timer 3 stop (TW3A instruction)
Prescaler selected for count source
b3 b0
01
0
Timer control register W3
✕
✕
➂ Set Timer Value
Timer 3 count time is set. (The formula is shown ❈A below.)
Timer 3 reload register R3
“52
16
”
Timer count value 82 set (T3AB instruction)
➃ Clear Interrupt Request
Timer 3 interrupt activated condition is cleared.
Timer 3 interrupt request flag T3F
“0”
Timer 3 interrupt activated condition cleared
(SNZT3 instruction)
Note when the interrupt request is cleared
When ➃ is executed, considering the skip of the next instruction according to the
interrupt request flag T3F, insert the NOP instruction after the SNZT3 instruction.
b3 b0
011
➄ Start Timer 3 Operation
Timer 3 and prescaler temporarily stopped are restarted.
Timer control register W3
Timer 3 operation start (TW3A instruction)
Prescaler operation start (TW1A instruction)
✕
b3 b0
11
Timer control register W1
✕✕
b3 b0
1
➅ Enable Interrupts
The timer 3 interrupt which is temporarily disabled is enabled.
Interrupt control register V2
Interrupt enable flag INTE
“1”
Timer 3 interrupt occurrence enabled
(TV2A instruction)
All interrupts enabled (EI instruction)
✕✕✕
Constant period interrupt execution start
❈A The prescaler dividing ratio and time 3 count value to make the interrupt occur every 1 ms are set as follows.
1 ms ≅ (4.0 MHz) ✕ 3 ✕ 16 ✕ (82+1)
–1
System clock Instruction
clock
Prescaler
dividing
ratio
Timer 3
count
value
“✕”: it can be “0” or “1.”