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4513/4514 Group User’s Manual
HARDWARE
1-57
CLOCK CONTROL
The clock control circuit consists of the following circuits.
• System clock generating circuit
• Control circuit to stop the clock oscillation
Fig. 41 Clock control circuit structure
Table 23 Clock control register MR
Note : “R” represents read enabled, and “W” represents write enabled.
• Control circuit to switch the middle-speed mode and high-speed
mode
• Control circuit to return from the RAM back-up state
MR3
MR2
MR1
MR0
Clock control register MR
f(XIN) (high-speed mode)
f(XIN)/2 (middle-speed mode)
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
System clock selection bit
Not used
Not used
Not used
at reset : 10002 at RAM back-up : 10002
0
1
0
1
0
1
0
1
R/W
Instruction clock
MR3
1
0
RESET
Falling detected
Ports P00, P01
Ports P02, P03
Ports P10, P11
Ports P12, P13
Multi-
plexer
K0
0,K01,K02,K03
Counter
Wait time (Note)
control circuit
Software
start signal
R
S
Q
POF instruction
XIN
XOUT
I12
0
“L” level
1
P30/INT0
Key-on wake up control register
I2
2
0
1
P31/INT1
Oscillation
circuit
Division circuit
(divided by 2)
Internal clock
generation circuit
(divided by 3)
“H” level
“L” level
“H” level
Note: The wait time control circuit is used to generate the time required to stabilize the f(XIN) oscillation.
System clock
FUNCTION BLOCK OPERATIONS