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ROM-IPL
1. An 8KB ROM
(2764
or
mask
ROM
equivalent)
is
used
for the
ROM-IPL.
2.
When
the
system
reset
signal
turns from
low to
high
state
after
power
on, the
main
CPU
starts
to
operate
At
this
stage,
the
ROM-IPL
is
addressed.
3. The CPU
starts
from
address
OOOOIROM
address
10000)
4. The
main
CPU
sets
the
sub-CPU
reset
signal from
low to
high
state
as it
goes
out of its
initial
state
via the
memory
mapper
and the
sub-CPU
starts
to
operate.
At
this
point,
the
ROM-IPL
is
addressed
by the
sub-CPU.
5.
Address
0000
of the
sub-CPU
is ROM
address
(0000)
The
memory
area
above
ROM
address
(1000)
cannot
be
used
by the
sub-CPU
because
the mam CPU
initial
program
has
been loaded
there.
2-2.
SD1
(SYSTEM
LOADING
&
CP/M)
SD1
determines
which
operating
system
ts in
use.
The
system
is
loaded
in the
CP/M
(Control
Program
for
Micro-
processors)
mode.
MZ3500
Mam
CPU
logical
address
(during
IPL
operation)
Logical
address
of the
sub-CPU
ROM
physical
address
OfFF
0800
0000
1
FFF
1
800
1
7FF
1
OOP
OFFF
0800
07FF
0000
1
FFF
1
800
I
7FF
1
OOP
OFFF
0800
07FF
0000
ROM IPL
MS1
= 0( L)
MSO=l(Hj
MAIN
CPU
r r
F?'
f. ft f
r
^
n
RAMicnu:
4
3
i
\
\
>
\
x
\
V
\
^ \
\ \
\
\
\
\
\ \
\
\
\ \
\
\
\ \
\ \
\ \
RAM sn
RAM SA
KAM«.(IH) 2000
1FFF
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