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MZ3500
(2)
640 x 400
bits
display
mode
fH =
20.92
kHz
fV =
47.3
Hz
X
: Y : 1 : 1
Dot
clock
(OD)
2XCCLK
Horizontal
display
time
HFP
HS
HBP
Vertical
display
time
VFP
VP
VBP
GDC-1
(80
digits)
Character
display
(40
digits)
(19
66MHz)
(9
83
MHz)
(4.9152MHz)
(2.4575MHz)
32
55^s
80
Chr.
/40
Chr.
4.88fjs
4^is
6 5ys
19.16ms
0.527ms
0.24
ms
1.198ms
GDC-2
8
bits
19.66MHz
(50.86ns)
4.9152MHz (203.45ns)
-
«-
*~
(tREF=0.6ms)
-
-
-
«-
-
graphic)
16
bits
9.83MHz (101
92ns)
24575MHz (406 9ns)
-
-
5
Chr.
*~
(tREF
=
1.23ms)
-
-
-
-
-
Total
rasters:
441
rasters
Display
rasters
400
rasters
(3) CRT
synchronizing
signal
specification
(400
raster
CRT)
1.
Horizontal
synchronization frequency
(fH):
20.92kHz
2.
Vercial synchronization frequency (fV): 47.3Hz
3.
Total
rasters:
441
rasters
4.
Rasters
used:
400
rasters
5.
Display
dots:
640 x 400
dots
6. Dot
clock:
(19.66MHz)
7.
Timing
9. HS, VS, and
VIDEO
signals
are
supplied
from
the LS
type
TTL 1C
(totem
pole)
6)
Setup
of GCD
master/slave
(1)
Master/slave setup
by
combination
^^•v^^
Character
^^•\^^
GDC
Graphic
^^^^
GDC
^"\^
Without
VRAM
PWB
8 bit
structure
48K
byte
200
rasters
16-bit
structure
96 K
byte
48K
byte
400
rasters
40
digits
Character
Character
Character
80
digits
Character
Ch3rai.te'
Graphic
Master
should
be
setup
in the
above
i.ia.
(2)
I/O
signal
switching
!
VFP:
11
rasters
(0.5ms)
VS-
5
rasters
(0.24ms)
VBP-
25
rasters
(1.2ms)
8.
Output
method
HS, VS. and
VIDEO
are
indpendent
outputs.
PIT A ft to
(8255.PB7
)
fiQ /I p ,, ,. ,
fc
(CSP-2)
VSYNC
Switching
Circuit