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Register-Level Programming Chapter 4
Lab-NB User Manual 4-48 © National Instruments Corporation
To program the counters, use the following programming sequence:
a. Write 70 (hex) to the Counter A Mode Register (select counter A1, mode 0). This step sets
the output of counter A1 (OUTA1) low, which in turn enables EXTTRIG; that is, the first
rising edge on EXTTRIG after OUTA1 goes low starts the DAQ sequence.
b. Write the least significant byte of (M-1), where M is the sample count, to the Counter A1
Data Register.
c. Write the most significant byte of (M-1), where M is the sample count, to the Counter A1
Data Register.
After completing this programming sequence, counter A1 is configured to count A/D conversion
pulses and EXTTRIG input is enabled.
6. Service the DAQ operation.
Once the DAQ operation is started by a rising edge on the EXTTRIG input, A/D conversions are
initiated by falling edges on the EXTCONV* input. The operation must be serviced by reading
the A/D FIFO Register every time an A/D conversion result becomes available. To service the
DAQ, perform the following sequence until the desired number of conversion results has been
read:
a. Read the Status Register (8-bit read).
b. If the DAVAIL bit is set (bit 0), read the A/D FIFO Register to obtain the result.
Interrupts can also be used to service the DAQ operation. Interrupts are discussed later in this
chapter.
Two error conditions may occur during a DAQ operation: an overflow error or an overrun error.
These error conditions are reported through the Status Register and should be checked every time
the Status Register is read to check the DAVAIL bit.
An overflow condition occurs if more than 16 A/D conversions have been stored in the A/D
FIFO without the A/D FIFO being read; that is, the A/D FIFO is full and cannot accept any more
data. This condition occurs if the software loop reading the A/D FIFO Register is not fast
enough to keep up with the A/D conversion rate. When an overflow occurs, at least one A/D
conversion result is lost. An overflow condition has occurred if the OVERFLOW bit in the
Status Register is cleared.
An overrun condition occurs if a second A/D conversion is initiated before the previous
conversion is finished. This condition may result in one or more missing A/D conversions. This
condition occurs if the sample interval is too small (sample rate is too high). An overrun
condition has occurred if the OVERRUN bit in the Status Register is low. The minimum
recommended sampling interval on the Lab-NB is 16 µsec.
Both the OVERFLOW and OVERRUN bits in the Status Register are reset by writing to the A/D
Clear Register.