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Chapter 4 Register-Level Programming
© National Instruments Corporation 4-37 Lab-NB User Manual
1. Select analog input channel and gain.
The analog input channel and gain are selected by writing to the A/D Configuration Register.
See the A/D Configuration Register bit description earlier in this chapter for gain and analog
input channel bit patterns. Set up the bits as given in the A/D Configuration Register bit
description, and write to the A/D Configuration Register.
The A/D Configuration Register needs to be written to only when the analog input channel, gain
setting, input mode (unipolar/bipolar), scanning mode, or interrupt enable bits need to be
changed.
2. Initiate an A/D conversion.
An A/D conversion can be initiated by a high-to-low transition on the counter A0 output
(OUTA0). Alternatively, a conversion can be performed by forcing a high-to-low transition on
EXTCONV*. To perform a single conversion with the onboard counters, use the following
programming sequence. All values are given in hexadecimal.
1. Write 38 to the Counter A Mode Register (8-bit write). This causes OUTA0 to be set high.
2. Write 30 to the Counter A Mode Register (8-bit write). This causes OUTA0 to be set low.
3. Write 38 to the Counter A0 Data Register (8-bit write). This causes OUTA0 to be set high.
Once an A/D conversion is initiated, the ADC stores the result in the A/D FIFO at the end of its
conversion cycle or after a rising edge on OUTA0, whichever occurs later. In case of
EXTCONV* initiating the conversion, OUTA0 and OUTA1 must both be set high.
3. Read the A/D conversion result.
A/D conversion results are obtained by reading the A/D FIFO Register. Before you read the A/D
FIFO, however, you must read the Status Register to determine whether the A/D FIFO contains
any results.
To read the A/D conversion results, complete these steps:
1. Read the A/D Status Register (8-bit read).
2. If the DAVAIL bit is set (bit 0), then read the A/D FIFO Register to obtain the result.
Reading the A/D FIFO Register removes the A/D conversion result from the A/D FIFO. The
binary modes of the A/D FIFO output are explained later.
The DAVAIL bit indicates whether one or more A/D conversion results are stored in the A/D
FIFO. If the DAVAIL bit is cleared, the A/D FIFO is empty and reading the A/D FIFO Register
returns meaningless data. Once an A/D conversion is initiated, the DAVAIL bit should be set
after 12 µsec or after a rising edge on OUTA0, whichever occurs later. If EXTCONV* is being