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Configuration and Installation Chapter 2
Lab-NB User Manual 2-24 © National Instruments Corporation
Figure 2-18 shows the timing requirements for the GATE and CLK input signals and the timing
specifications for the OUT output signals of the 8253.
t
sc
t
pwh
t
pwl
t
gsu
t
gh
t
gwh
t
gwl
t
outc
t
outg
CLK
GATE
OUT
V
OH
V
IH
V
IL
V
IH
V
OL
V
IL
t
sc
t
pwh
t
pwl
t
gsu
t
gh
t
gwh
t
gwl
t
outg
t
outc
clock period
clock high level
clock low level
gate setup time
gate hold time
gate high level
gate low level
output delay from clock
output delay from gate
380 nsec min
230 nsec min
150 nsec min
100 nsec min
50 nsec min
150 nsec min
100 nsec min
300 nsec min
400 nsec min
Figure 2-18. General-Purpose Timing Signals
The GATE and OUT signals in Figure 2-18 are referenced to the rising edge of the CLK signal.