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Chapter 3 Theory of Operation
© National Instruments Corporation 3-11 Lab-NB User Manual
Each 8253 contains three independent 16-bit counter/timers and one 8-bit Mode Register. As
shown in Figure 3-6, counter group A is reserved for DAQ timing, and counter group B is free
for general use. The output of counter B0 can be used in place of the 1-MHz clock source on
counter A0 to allow clock periods greater than 65,536 µsec. All six counter/timers can be
programmed to operate in several useful timing modes. The programming and operation of the
8253 is presented in detail both in Chapter 4, Register-Level Programming, and in Appendix C,
AMD 8253 Data Sheet.
The 8253 for counter group A uses either a 1-MHz clock generated from the NuBus clock or the
output from counter B0, which has a 2-MHz clock source, for its timebase. The timebases for
counters B1 and B2 must be supplied externally through the 50-pin I/O connector. The 16-bit
counters in the 8253 can be diagrammed as shown in Figure 3-7.
CLK
GATE
OUT
Counter
Figure 3-7. Counter Block Diagram
Each counter has a CLK input pin, a GATE input pin, and an output pin labeled OUT. The 8253
counters are numbered 0 through 2, and their GATE, CLK, and OUT pins are labeled GATE N,
CLK N, and OUT N, where N is the counter number.