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Register-Level Programming Chapter 4
Lab-NB User Manual 4-50 © National Instruments Corporation
4. Clear the A/D circuitry.
Before the DAQ operation is started, the A/D FIFO must be emptied in order to clear any old
A/D conversion results. Empty the A/D FIFO after the counters are programmed because
programming the counters can cause spurious edges. Write 0 to the A/D Clear Register to empty
the FIFO (8-bit write) and to read from the A/D FIFO (16-bit read). Ignore the data obtained
while reading the A/D Clear Register. In pretrigger mode, a write to the A/D Clear Register also
sets the GATA1 bit low. A/D conversions are not counted until GATA1 is set high by a rising
edge on the EXTTRIG input.
5. Program counter A1 and enable EXTCONV* input.
Counter A1 of the 8253(A) Counter/Timer is used as a sample counter. The sample counter
counts the number of A/D conversions and disables conversions when the programmed count is
reached. The sample count must be less than or equal to 65,535. The minimum sample count is
2. EXTCONV* is enabled as soon as counter A1 is programmed.
To program the counters, use the following programming sequence.
a. Write 70 (hex) to the Counter A Mode Register (select counter A1, mode 0). This step sets
the output of counter A1 (OUTA1) low, which in turn, enables EXTCONV*; that is, falling
edges on EXTCONV* initiate A/D conversions.
b. Write the least significant byte of (M-1), where M is the sample count after the trigger to the
Counter A1 Data Register.
c. Write the most significant byte of (M-1), where M is the sample count after the trigger to the
Counter A1 Data Register.
After you complete this programming sequence, counter A1 is configured to count A/D
conversion pulses and EXTTRIG input is enabled. A/D conversions are initiated by falling
edges on EXTCONV* input, but the sample counter (counter A1) is not gated on until a rising
edge on the EXTTRIG input. After a rising edge on the EXTTRIG input is sensed, A/D
conversions remain enabled for the programmed count after which GATA1 is set low and
EXTCONV* input is disabled.
6. Service the DAQ operation.
Once the DAQ operation is enabled in step 5, A/D conversions are initiated by the falling edges
on the EXTCONV* input. The operation must be serviced by reading the A/D FIFO Register
every time an A/D conversion result becomes available. To service the data acquisition, perform
the following sequence until the GATA0 bit in the Status Register is set low:
a. Read the Status Register (8-bit read).
b. If the DAVAIL bit is set (bit 0), read the A/D FIFO Register to obtain the result.
Interrupts can also be used to service the DAQ operation. Interrupts are discussed later in this
chapter.