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Chapter 4 Register-Level Programming
© National Instruments Corporation 4-49 Lab-NB User Manual
Pretrigger Mode
The following programming steps are required for a DAQ operation in controlled acquisition
mode using EXTCONV*. In the following programming sequence, EXTTRIG is used as a
pretrigger signal; that is, A/D conversions are enabled but the sample count is not started until a
rising edge is detected on the EXTTRIG input. Data acquisition remains enabled for the
programmed count after the rising edge on the EXTTRIG input. Thus, data can be acquired
before and after the trigger (EXTTRIG).
1. Disable EXTCONV* and EXTTRIG input.
2. Select analog input channel and gain and select pretrigger mode.
3. Program counter A0.
4. Clear the A/D circuitry.
5. Program counter A1 and enable EXTCONV* and EXTTRIG input.
6. Service the DAQ operation.
Each of these programming steps is explained as follows.
1. Disable EXTCONV* and EXTTRIG input.
The EXTCONV* input can be disabled by setting the GATA0 bit low. The GATA0 bit is low
whenever OUTA1 is high, regardless of the settings for the PRETRIG or EXTTRIGEN bits in
the ADC Configuration Register or the EXTTRIG signal. Writing 78 (hex) to the counter A
Mode Register sets OUTA1 high. This write disables EXTCONV* and EXTTRIG input; that is,
any transitions on these two inputs are ignored.
2. Select analog input channel and gain and select pretrigger mode.
The analog input channel and gain are selected by writing to the A/D Configuration Register.
The SCANEN bit must be cleared for DAQ operations on a single channel. See the A/D
Configuration Register bit description earlier in this chapter for gain and analog input channel bit
descriptions. The PRETRIG bit must be set high and the EXTRIGEN bit must be set low during
this write to the A/D Configuration Register. These settings select pretrigger mode.
3. Program counter A0.
Since a high-to-low transition on the counter A0 output initiates an A/D conversion, counter A0
output must be programmed to a high state. This ensures that counter A0 does not cause any
A/D conversions.
Write 34 (hex) to the Counter A Mode Register (select counter A0, mode 2) to force OUTA0 to a
high state. This is an 8-bit operation.