Chapter 4 Register-Level Programming
© National Instruments Corporation 4-45 Lab-NB User Manual
7. Service the DAQ operation.
Once the DAQ operation is started by writing the most significant byte of the sample interval to
the Counter A0 Data Register, the operation must be serviced by reading the A/D FIFO Register
every time an A/D conversion result becomes available. To do this, perform the following
sequence until the desired number of conversion results has been read:
a. Read the Status Register (8-bit read).
b. If the DAVAIL bit is set (bit 0), then read the A/D FIFO Register to obtain the result.
Interrupts can also be used to service the DAQ operation. This topic is discussed later in this
chapter.
Two error conditions may occur during a DAQ operation: an overflow error or an overrun error.
These error conditions are reported through the Status Register and should be checked every time
the Status Register is read to check the DAVAIL bit.
An overflow condition occurs if more than 16 A/D conversions have been stored in the A/D
FIFO without the A/D FIFO being read; that is, the A/D FIFO is full and cannot accept any more
data. This condition occurs if the software loop reading the A/D FIFO Register is not fast
enough to keep up with the A/D conversion rate. When an overflow occurs, at least one A/D
conversion result is lost. An overflow condition has occurred if the OVERFLOW bit in the
Status Register is set.
An overrun condition occurs if a second A/D conversion is initiated before the previous
conversion is finished. This condition may result in one or more missing A/D conversions. This
condition occurs if the sample interval is too small (sample rate is too high). An overrun
condition has occurred if the OVERRUN bit in the Status Register is set. The minimum
recommended sampling interval on the Lab-NB is 16 µsec.
Both the OVERFLOW and OVERRUN bits in the Status Register are cleared by writing to the
A/D Clear Register.
External Timing Considerations for Multiple A/D Conversions
Two external timing signals, EXTTRIG and EXTCONV*, can be used for multiple A/D
conversions. EXTTRIG can be used to initiate a conversion sequence (posttrigger mode) or to
terminate an ongoing conversion sequence (pretrigger mode), and the EXTCONV* signal can be
used to time the individual A/D conversions from an external timing source. Chapter 2,
Configuration and Installation, contains the EXTTRIG and EXTCONV* signal specifications.
The posttrigger and pretrigger modes are described later in this chapter.
Using the EXTTRIG Signal to Initiate a Multiple A/D Conversion DAQ Operation
(Posttrigger Mode)
If the PRETRIG bit is cleared and the EXTTRIGEN bit is set in the ADC Command Register,
EXTTRIG functions as a start trigger for a multiple A/D conversion DAQ operation. In this
mode, referred to as posttriggering, the sample-interval counter is gated off until a low-to-high
edge is sensed on EXTTRIG. No samples are collected until EXTTRIG makes its low-to-high
transition. Transitions on the EXTCONV* line are also ignored until a low-to-high edge is
sensed on the EXTRIG followed by a low-to-high edge on EXTCONV* input.