National Instruments 653X Switch User Manual


 
Index
© National Instruments Corporation I-7 653X User Manual
O
optimizing transfer rates, E-1 to E-9
benchmark results, E-3 to E-9
AT-DIO-32HS (table), E-4
DAQCard-6533 for PCMCIA
(table), E-6
PCI-6534, E-6toE-7
PCI-7030/6533 with LabVIEW RT
(table), E-8
PCI-DIO-32HS (table), E-4 to E-5
PXI-6533 (table), E-5
PXI-6533 with LabVIEW RT (table),
E-8toE-9
PXI-6534 (table), E-7
maximum transfer rates, E-1 to E-2
obtaining fastest transfer rates, E-2
optional equipment for connecting
signals, C-7
P
pattern I/O, 2-17 to 2-26
connecting signals, 2-23 to 2-24
continuous or finite data transfer
continuous input, 2-21 to 2-22
continuous output, 2-22
DMA or interrupt transfers, 2-22
finite, 2-21
internal or external REQ source, 2-18
maximum transfer rate (table), E-3
monitoring data transfer, 2-23
port and timing controller combinations
(table), 2-17
programming, 2-24 to 2-26
continuous, in NI-DAQ, 2-25
LabVIEW/LabVIEW RT, 2-25
single buffer, in NI-DAQ, 2-24
REQ polarity, 2-18
specifications, A-3
timing diagrams, 3-1 to 3-3
external REQ signal source,
3-2to3-3
internal REQ signal source,
3-1to3-2
transfer direction, 2-18
transfer rate, 2-18 to 2-19
triggering data transfer, 2-19 to 2-21
pattern-matching trigger (input only),
2-20 to 2-21
start and stop trigger, 2-20 to 2-21
start trigger, 2-19
stop trigger, 2-19 to 2-20
when to use (table), 2-1
width of data to transfer, 2-17
pattern-matching trigger
change detection, 2-29 to 2-30
input only, pattern I/O, 2-20 to 2-21
PCI-6534 device
benchmark results (table), E-6 to E-7
block diagram, D-4
installation, 1-6
support for DMA transfers (table), E-2
PCI-7030/6533 device
benchmark results (table), E-8
block diagram, D-3
installation, 1-6
PCI-DIO-32HS
benchmark results (table), E-4 to E-5
block diagram, D-3
installation, 1-6 to 1-7
support for DMA transfers (table), E-2
PCLK<1..2> signal
burst input timing diagrams
default input timing diagram
(figure), 3-8
PCLK reversed (figure), 3-10
transfer example (figure), 3-6
burst output timing diagrams
output timing diagram (figure), 3-9
PCLK reversed (figure), 3-11