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Chapter 3 Timing Diagrams
© National Instruments Corporation 3-11 653X User Manual
Figure 3-8.
Burst Output Timing Diagram (PCLK Reversed)
Parameter Description Minimum Maximum
Input Parameters
t
rs
Setup time from REQ valid to PCLK 12 —
t
rh
Hold time from PCLK to REQ invalid 0 —
Output Parameters
t
pc
PCLK cycle time 50 700
1
t
pw
PCLK high pulse duration t
pc
/2 – 5t
pc
/2 + 5
t
pa
PCLK to ACK valid — 18
t
ah
Hold time from PCLK to ACK invalid 3 —
t
pdo
PCLK to output data valid — 28
t
doh
Hold time from PCLK to output data
invalid
4 —
t
dis
Setup time from input data valid to PCLK 0 —
t
dih
Hold time from PCLK to input data invalid 0 —
1
t
pc
= programmable delay from 100 to 700 ns, or 50 ns if programmable delay is 0. Timebase stability for the board
20 MHz clock source is 50 ppm.
All timing values are in nanoseconds.
PCLK
ACK
Data Out Valid
REQ
t
rs
t
pa
t
pdo
t
pw
t
pc
t
doh
t
rh
t
ah