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Chapter 3 Timing Diagrams
© National Instruments Corporation 3-9 653X User Manual
Figure 3-6. Burst Output Timing Diagram (Default)
Parameter Description Minimum Maximum
Input Parameters
t
pc
PCLK cycle time 50 —
t
pw
PCLK high pulse duration 20 —
t
pl
PCLK low pulse duration 20 —
t
rs
Setup time from REQ valid to PCLK
falling edge
1—
t
rh
Hold time from PCLK to REQ invalid 0 —
Output Parameters
t
pa
PCLK to ACK valid — 22
t
ah
Hold time from PCLK to ACK invalid 3 —
t
pdo
PCLK to output data valid — 28
t
doh
Hold time from PCLK to output data
invalid
5—
All timing values are in nanoseconds.
PCLK
ACK
Data Out Valid
REQ
t
rs
t
pa
t
pdo
t
pw
t
pl
t
pc
t
rh
t
ah
t
doh